Communication devices of various kinds rely on various circuitry to control parameters of wireless communication. Part of this process includes tuning the antenna portion of the communication device to be able to communicate at particular frequencies. Similarly, various circuitry relies on receipt of certain clock signals at particular frequencies to facilitate proper operation of the circuit at designated frequency bands. Additionally, there can be an advantage to having such clock signals being issued at harmonics or sub-harmonics of a given fundamental frequency. This is especially beneficial where multiple clock frequencies can be derived from the same high speed oscillators.
Accordingly, in such radio/high frequency clocking systems, there is a need to provide various circuit blocks with an oscillating signal with a frequency that is an odd sub-harmonic of a fundamental oscillating signal, i.e., clock, using low power and a compact implementation. In addition to a lower output frequency, multiple output phases can allow for a variety of signal processing capabilities in the high speed circuits and systems. Current solutions to saving the external bill of materials (BOM) for modern radio frequency (RF) transceivers operating at low frequency exist with large power and area analog filters. In one approach, extensive on-chip filtering aided by process and temperature calibration/compensation can be applied using clocks operating with single phase logic, but this approach is prone to imbalance at high frequency. In another approach, RF filtering using high quality factor (Q) external components are applied to reject harmonics of a local oscillator (LO) signal, but this approach is prone to component variation for the external filters. Moreover, both of these techniques increase the overall cost of the solution in power, area, and/or external components.